With the scaling of semiconductor process technologies, threshold voltages of metal oxide semiconductor circuits are typically being reduced with reductions in supply voltages in order to maintain circuit performance. Lower transistor threshold voltages lead to significant increases in leakage current due to the exponential nature of sub-threshold conductance. Higher leakage currents increase power dissipation which is undesirable for many semiconductor circuit applications. Higher leakage currents can be particularly problematic for mobile and handheld applications, for example.
One approach to addressing this issue has been to use dual threshold voltage and/or substrate bias techniques. In a dual threshold voltage approach, certain devices on a particular integrated circuit are designed and fabricated to have a first, low threshold voltage, while other devices on the same integrated circuit are designed and fabricated to have a second, higher threshold voltage. In this manner, devices that cannot tolerate the higher leakage current characteristic of lower threshold voltages can be selected to have higher threshold voltages.
In order to implement a dual threshold voltage scheme, additional gates are added to provide a transition from low threshold voltage areas to higher threshold voltage areas. The additional gates take up valuable semiconductor real estate. Further, circuit performance and power dissipation can be compromised using this approach.
Where a substrate bias technique is used, during an active mode, a control circuit applies a voltage to transistor bodies to zero- or reverse-bias the bodies with respect to the transistors. Upon entering a standby mode, the control circuit changes the substrate bias voltage to cause a reverse bias or deepen an existing reverse bias in the transistor bodies. In this manner, the threshold voltage of the transistors are increased during a standby mode to reduce or cut off leakage current.
A disadvantage of this approach is that a large change in body bias is required to change the transistor threshold voltages by even a small amount. Further, when changing from active mode to standby mode and vice versa, large capacitances in transistor wells are switched from one voltage to another. Thus, significant power is dissipated during each mode transition. An increase in design complexity may also result from implementing such a substrate bias technique.
In a paper presented at the IEEE Custom, Integrated Circuit Conference in August of 1997 entitled, "A Gate-Level Leakage Power Reduction Method for Ultra-Low-Power CMOS Circuits," by Jonathan P. Halter and Farid N. Najm of the ECE Dept. and Coordinated Science Lab. at the University of Illinois at Urbana-Champaign ("the Halter reference"), another approach to reducing leakage power is proposed. The Halter reference describes an approach wherein, for a multi-gate logic circuit, an algorithmically determined input vector is applied to the multi-gate logic circuit during an idle period to reduce leakage power of the multi-gate logic circuit during the idle period.
The algorithm described in the Halter reference for determining the input vector to be applied to the multi-gate logic depends on being able to estimate the leakage associated with a candidate vector. As described in the Halter reference, this can be done using a circuit-level simulator or by building library models for logic gates that give the leakage current drawn by a gate for each of its input combinations.
As admitted by Halter, the search problem for the vector that gives the least leakage power is a very difficult one because of the potentially huge size of the search space. With this in mind, Halter looks not for a vector that minimizes leakage current, but rather only for a vector that gives a significantly lower value of leakage and which can be found efficiently using a described algorithm.
The algorithm described in the Halter reference for selecting such an input vector is based on a process of random sampling. Randomly chosen vectors are applied to the circuit, the leakage due to each is monitored and the vector that gives the least observed leakage out of those selected is used. Thus, according to Halter, the quality of the solution in terms of the particular input vector selected is related to the number of randomly chosen vectors that are tested.
An issue with the approach described in the Halter reference is that potential input vectors are randomly chosen to find one that reduces leakage. The only way to know whether a chosen vector is good or bad is to choose and test many other vectors. For complex circuits including hundreds or thousands of gates, this task can require significant time. Further, there is virtually no way to know whether another input vector that has not been tested might provide leakage reduction superior to the chosen vector. The chance of choosing the input vector that provides the maximum leakage reduction possible for a given circuit using the approach described in Halter is very small, particularly for large circuits having many inputs.